Parasitic capacitance associated with the conductive elements of densely packed integrated circuits can affect device performance and result in unacceptable and unpredictable circuit performance. For example, such capacitance can significantly slow down the circuit operation and, particularly for analog circuits, can produce cross talk between conductors. It is desirable to predict the parasitic capacitance of a conducting element within an integrated circuit so that established design criteria will be based on accurate capacitance models. Excessive capacitance can be corrected in the design before the integrated circuit is fabricated.
Many methods exist for calculating the parasitic capacitance of a conductor within an integrated circuit. The parasitic capacitance of a conducting wire is a function of the elements comprising the structure which includes the conducting wire. A number of parameters describing the structure may be used to calculate the parasitic capacitance. The current art provides methods which use these parameters, and a matrix problem solving technique, to calculate the parasitic capacitance of a conductor within an integrated circuit.
The use of a matrix to calculate parasitic capacitance, for a single set of parameters describing a single conductive element, is a time consuming procedure. A typical integrated circuit contains a multitude of conductive elements in a number of various configurations. To calculate the parasitic capacitance for a multitude of conductive elements, each described by a different set of parameters representing a specific structure, may require considerable time. Thus, the use of a matrix procedure, for calculating the parasitic capacitance for an entire integrated circuit, may be unsuitable for chip and circuit design which involves up to millions of conductors within a single integrated circuit.
Other methods are available to calculate parasitic capacitance without using matrices. These methods may not be as accurate as desired. The deficiencies of the conventional methods for determining parasitic capacitance show that a need still exists for an improved method and apparatus for calculating parasitic capacitance between conductors of an integrated circuit.